Xilinx Vivado Design Suite 2024.2 (Windows | Linux | English)

What's new in Vivado 2024.2 - Date: Nov 18, 2024

Advanced Flow for Place-and-Route of All Versal Devices
- Automatic partition-based placement and parallel P&R
- Reduces congestion and improves routability for fast design closure
- Default flow for all Versal devices
Enabling Top-Level RTL Flows for Versal Devices
- Configure key components like NoC and transceivers from top-level RTL
- Enables programmable logic developers to stay in a RTL-centric design environment
Segmented Configuration for Fast Boot of Versal Processing Subsystem (PS)
- PS boots first, deferring configuration of programmable logic (PL)
- Enables fast bring-up of OS with DDR
- Meets diverse boot sequence requirements
Ease-of-Use Features
- New real-time preset for MicroBlaze V
- In-line HDL of utility IP allows faster IP load and configuration
- Enhanced DFX floorplan visualization & DFX summary report
- New utility for PDI debug (decode and analyze boot configuration errors
- GUI enhancements for Pblocks during floorplanning



Vivado Design Suiteis a software suite designed by Xilinx for the design, synthesis and analysis of HDL for its line of FPGAs and SoCs. Vivado Design Suite includes many tools, like Vivado, Vitis, Vitis HLS and many others. The Vivado Design Suite offers many ways to accomplish the tasks involved in Xilinx FPGA design and verification. In addition to the traditional RTL to bitstream FPGA design flow, the Vivado Design Suite provides new system-level integration flows that focus on IP-centric design. Design analysis and verification is enabled at each stage of the flow. Design analysis features include logic simulation, I/O and clock planning, power analysis, timing analysis, design rule checking (DRC), visualization of design logic and implementation results, and programming and debugging. The entire solution is integrated within a graphical user interface (GUI) known as the Vivado Integrated Design Environment (IDE). The Vivado IDE provides an interface to assemble, implement, and validate the design and the IP. In addition, all flows can be run using the Tcl application programming interface (API). Tcl commands can be interactively entered using the Tcl prompt or saved in a Tcl script. You can use Tcl scripts to run the entire design flow, including design analysis, or to run just part of the flow
Vivado Lab Editionis a compact, and standalone product targeted for use in the lab environments. It provides for programming and logic/serial IO debug of all Vivado supported devices. Lab Edition requires no certificate or activation license key.
Vivado Hardware Server enables Vivado Design tools to communicate with a remote target system.

Vivado QuickTake Tutorials

Short "How To" videos on utilizing the Xilinx Vivado Design Suite

Accelerating the development of smarter systems requires levels of automation that go beyond RTL level design. With the introduction of the Vivado Design Suite, Xilinx delivers a SoC-strength, IP-and system centric, next generation development environment that has been built from the ground up to address the productivity bottlenecks in system-level integration and implementation
Xilinxdevelops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs, and the ACAP, designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent, and connected world of the future
Xilinx is now part of AMD.AMD now has the industry's broadest product portfolio and a highly complementary set of technologies, reaching customers in a diverse set of markets. Together, AMD and Xilinx leverage the right engine for the right workload to address the compute needs for our customers.